Landing: 0ef314fa24c8
Project / Subsystem
gcc / gcc/risc-v
Date
2026-08-23
Author
Jeff Law
Commit
0ef314fa24c8526f2c3db8dd564d214cf2d6a3b7
Source
github
Perf win
No
Breaking
No
All attributes
- project
- gcc
- subsystem
- gcc/risc-v
- patch_id
- —
- commit_hash
- 0ef314fa24c8526f2c3db8dd564d214cf2d6a3b7
- source_type
- github
- headline
- Allow RISC-V 't' registers in scan-assembler tests
- tldr
- Expands RISC-V assembly tests to include 't' registers for better coverage.
- author
- Jeff Law
- outcome
- committed
- performance_win
- false
- breaking_change
- false
- series_id
- —
- series_parts
- []
- tags
-
- • risc-v
- • testing
- • asm
- discussion_id_link
- —
- bugzilla_pr
- —
- date
- 2026-08-23T00:00:00.000Z
This commit updates RISC-V scan-assembler tests to allow the use of ‘t’ registers, which were previously excluded. The change broadens testing coverage by ensuring that assembly directives and register aliases are correctly handled across different RISC-V core configurations, particularly on the K1 design. This addresses a potential oversight in register alias handling that could lead to test failures.