Landing: 03c6b959d62b
Project / Subsystem
gcc / risc-v
Date
2026-08-23
Author
Pan Li
Commit
03c6b959d62b560c75a979d130537dc15be5ae6a
Source
github
Perf win
No
Breaking
No
All attributes
- project
- gcc
- subsystem
- risc-v
- patch_id
- —
- commit_hash
- 03c6b959d62b560c75a979d130537dc15be5ae6a
- source_type
- github
- headline
- RISC-V: Add test cases for vwmulsu.vx register overlap
- tldr
- Adds numerous test cases for RISC-V `vwmulsu.vx` instruction with register overlap.
- author
- Pan Li
- outcome
- committed
- performance_win
- false
- breaking_change
- false
- series_id
- —
- series_parts
- []
- tags
-
- • risc-v
- • rvv
- • testing
- • optimization
- discussion_id_link
- —
- bugzilla_pr
- —
- date
- 2026-08-23T00:00:00.000Z
This commit significantly expands the test suite for the RISC-V vector instruction vwmulsu.vx by adding many new test cases. These tests specifically target scenarios involving register group overlap, ensuring the compiler correctly handles these complex cases for various data types and vector lengths. This aims to improve the robustness of vector code generation.