Landing: f56a404195fa
Project / Subsystem
gcc / risc-v
Date
2026-08-23
Author
Pan Li
Commit
f56a404195fa986d867f015f85f4f6fcbdc4c656
Source
github
Perf win
Yes
Breaking
No
All attributes
- project
- gcc
- subsystem
- risc-v
- patch_id
- —
- commit_hash
- f56a404195fa986d867f015f85f4f6fcbdc4c656
- source_type
- github
- headline
- RISC-V: Allow RVV register overlap for vwmulsu.vx
- tldr
- Enables register overlap for RISC-V `vwmulsu.vx` instruction.
- author
- Pan Li
- outcome
- committed
- performance_win
- true
- breaking_change
- false
- series_id
- —
- series_parts
- []
- tags
-
- • risc-v
- • rvv
- • optimization
- discussion_id_link
- —
- bugzilla_pr
- —
- date
- 2026-08-23T00:00:00.000Z
This commit allows register overlap for the RISC-V vector instruction vwmulsu.vx. Similar to other widening vector multiplication instructions, this change enables the reuse of vector registers, which can lead to more efficient code generation. The change modifies the vector constraint in the GCC target configuration for RISC-V.