Landing: c69c5e7b8e08
Project / Subsystem
gcc / risc-v
Date
2026-08-27
Author
Pan Li
Commit
c69c5e7b8e08b99701054c19ae26730979ebb78f
Source
github
Perf win
Yes
Breaking
No
All attributes
- project
- gcc
- subsystem
- risc-v
- patch_id
- —
- commit_hash
- c69c5e7b8e08b99701054c19ae26730979ebb78f
- source_type
- github
- headline
- RISC-V vector instructions allow register group overlap.
- tldr
- RISC-V vector instructions vwmacc.vx and vwmaccu.vx now support register group overlap.
- author
- Pan Li
- outcome
- committed
- performance_win
- true
- breaking_change
- false
- series_id
- —
- series_parts
- []
- tags
-
- • risc-v
- • vector
- • optimization
- discussion_id_link
- —
- bugzilla_pr
- —
- date
- 2026-08-27T00:00:00.000Z
The RISC-V vector extension (RVV) has been updated to allow register group overlap for the vwmacc.vx and vwmaccu.vx instructions. This change enables more flexible register allocation and potentially better performance by allowing these instructions to use registers that might otherwise be considered overlapping.
New test cases have been added to verify this functionality across various data types and vector sizes, ensuring correct behavior and preventing regressions.