Landing: 68ce5148b9b0
Project / Subsystem
gcc / risc-v
Date
2026-08-28
Author
Pan Li
Commit
68ce5148b9b08d00043b11dccd37589c69b7f61d
Source
github
Perf win
Yes
Breaking
No
All attributes
- project
- gcc
- subsystem
- risc-v
- patch_id
- —
- commit_hash
- 68ce5148b9b08d00043b11dccd37589c69b7f61d
- source_type
- github
- headline
- RISC-V: Allow RVV register overlap for vwmaccsu.vx
- tldr
- RISC-V vwmaccsu.vx instruction now supports register overlap, similar to other widen ternary instructions.
- author
- Pan Li
- outcome
- committed
- performance_win
- true
- breaking_change
- false
- series_id
- —
- series_parts
- []
- tags
-
- • risc-v
- • vector extension
- • optimization
- discussion_id_link
- —
- bugzilla_pr
- —
- date
- 2026-08-28T00:00:00.000Z
This change extends the support for register overlap to the RISC-V vwmaccsu.vx instruction. By leveraging the Wvr constraint in the vector-masking table, this modification aligns the behavior of vwmaccsu.vx with similar instructions like vwmacc[u].vx, allowing for more flexible and potentially optimized register usage.