Landing: e128159fd670
Project / Subsystem
gcc / risc-v
Date
2026-08-29
Author
Luke Zhuang
Commit
e128159fd67096ff3354b323b974d06e55e27e3d
Source
github
Perf win
No
Breaking
No
All attributes
- project
- gcc
- subsystem
- risc-v
- patch_id
- —
- commit_hash
- e128159fd67096ff3354b323b974d06e55e27e3d
- source_type
- github
- headline
- RISC-V: Add RTL tests for slliw shifted bitfield constraints
- tldr
- Adds RTL tests to verify slliw shifted bitfield constraints in RISC-V.
- author
- Luke Zhuang
- outcome
- committed
- performance_win
- false
- breaking_change
- false
- series_id
- —
- series_parts
- []
- tags
-
- • risc-v
- • rtl
- • compiler
- • testing
- discussion_id_link
- —
- bugzilla_pr
- —
- date
- 2026-08-29T00:00:00.000Z
New RTL tests are added for the RISC-V shifted-bitfield SLLIW constraints. These tests specifically cover nonzero start-bit and high-32-bit mask cases, ensuring they are not incorrectly rewritten to SLLIW instructions.