Landing: 51f95fed1ac7
Project / Subsystem
binutils / risc-v
Date
2026-09-01
Author
Kuan-Lin Chen <kuanlinchen@sourceware.org>
Commit
51f95fed1ac7cd44ebf18193e52f77c75c9dc7ce
Source
public_inbox
Perf win
No
Breaking
No
All attributes
- project
- binutils
- subsystem
- risc-v
- patch_id
- —
- commit_hash
- 51f95fed1ac7cd44ebf18193e52f77c75c9dc7ce
- source_type
- public_inbox
- headline
- RISC-V: Add support for XAndesVSIntLoad extension
- tldr
- Binutils now supports the RISC-V XAndesVSIntLoad extension for vector load operations.
- author
- Kuan-Lin Chen <kuanlinchen@sourceware.org>
- outcome
- committed
- performance_win
- false
- breaking_change
- false
- series_id
- —
- series_parts
- []
- tags
-
- • risc-v
- • vector instructions
- • assembler
- discussion_id_link
- —
- bugzilla_pr
- —
- date
- 2026-09-01T00:00:00.000Z
This commit adds support for the RISC-V XAndesVSIntLoad extension, which handles vector load operations for INT4 data into 8-bit elements. The changes update BFD for ELF compatibility, GAS for assembler syntax and tests, and the opcode library for instruction recognition. This enables the use of specialized vector load instructions for improved data handling efficiency.