Landing: b933df353a14
Project / Subsystem
gcc / risc-v
Date
2026-09-01
Author
Pan Li
Commit
b933df353a14604fd7fbd32c6623afcfc90e5f2b
Source
github
Perf win
No
Breaking
No
All attributes
- project
- gcc
- subsystem
- risc-v
- patch_id
- —
- commit_hash
- b933df353a14604fd7fbd32c6623afcfc90e5f2b
- source_type
- github
- headline
- RISC-V: Allow RVV register overlap for vwmaccus.vx
- tldr
- Enables register overlap for RISC-V vector multiply-accumulate instruction, removing test case xfails.
- author
- Pan Li
- outcome
- committed
- performance_win
- false
- breaking_change
- false
- series_id
- —
- series_parts
- []
- tags
-
- • risc-v
- • vector processing
- • optimization
- discussion_id_link
- —
- bugzilla_pr
- —
- date
- 2026-09-01T00:00:00.000Z
This change enables register overlap for the RISC-V vector instruction vwmaccus.vx, similar to other widen ternary vx instructions. By leveraging the Wvr constraint in the machine description, the compiler can now allow these registers to overlap, which previously caused related test cases to fail. This allows for more flexible register allocation and simplifies testing.