Landing: edcd07b896e8
Project / Subsystem
binutils / risc-v
Date
2026-09-01
Author
Kuan-Lin Chen <kuanlinchen@sourceware.org>
Commit
edcd07b896e8fa4a984a8fa88b0aaf0d336665a5
Source
public_inbox
Perf win
No
Breaking
No
All attributes
- project
- binutils
- subsystem
- risc-v
- patch_id
- —
- commit_hash
- edcd07b896e8fa4a984a8fa88b0aaf0d336665a5
- source_type
- public_inbox
- headline
- RISC-V: Add support for XAndesVBFHCvt extension
- tldr
- Binutils now supports the RISC-V XAndesVBFHCvt extension for vector BF16 and FP32 conversion instructions.
- author
- Kuan-Lin Chen <kuanlinchen@sourceware.org>
- outcome
- committed
- performance_win
- false
- breaking_change
- false
- series_id
- —
- series_parts
- []
- tags
-
- • risc-v
- • floating-point
- • vector instructions
- • assembler
- discussion_id_link
- —
- bugzilla_pr
- —
- date
- 2026-09-01T00:00:00.000Z
This commit adds support for the RISC-V XAndesVBFHCvt extension, enabling vector conversion instructions between BF16 and FP32 formats. Changes include updates to BFD for ELF handling, GAS for assembler syntax and tests, and the opcode library for instruction definitions. This allows for more efficient mixed-precision floating-point computations.