Landing: 9c32008587df

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Project / Subsystem

gcc / gcc/i386

Date

2026-09-02

Author

Haochen Jiang

Commit

9c32008587df0c4decf842d9685c5507462bc217

Source

github

Perf win

Breaking

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All attributes

project: gcc
subsystem: gcc/i386
patch_id: —
commit_hash: 9c32008587df0c4decf842d9685c5507462bc217
source_type: github
headline: Support BSR0 register
tldr: Adds support for the BSR0 register, treating it similarly to TMM registers for future extensibility.
author: Haochen Jiang
outcome: committed
performance_win: false
breaking_change: false
series_id: —
series_parts: []
tags: • gcc
• i386
• ACEv1
• register
• compiler
discussion_id_link: —
bugzilla_pr: —
url: https://github.com/gcc-mirror/gcc/commit/9c32008587df0c4decf842d9685c5507462bc217
date: 2026-09-02T00:00:00.000Z

This commit introduces support for the BSR0 register, part of the ACEv1 ISA. It treats BSR registers similarly to TMM registers, allocating space for future extensions and enabling register allocation. Changes include updates to register class maps, debugger register maps, conditional register usage, and machine description files, ensuring the BSR0 register is recognized and managed by the compiler.