Landing: 63fa52f94b89

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Project / Subsystem

gcc / risc-v

Date

2026-09-02

Author

Pan Li

Commit

63fa52f94b89eefb8d56829d53bb8a59015f0bb6

Source

github

Perf win

Breaking

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All attributes

project: gcc
subsystem: risc-v
patch_id: —
commit_hash: 63fa52f94b89eefb8d56829d53bb8a59015f0bb6
source_type: github
headline: RISC-V: Allow register overlap for vwmaccu.vx undef instruction
tldr: RISC-V vector extension now allows register overlap for the `vwmaccu.vx` undef instruction.
author: Pan Li
outcome: committed
performance_win: false
breaking_change: false
series_id: —
series_parts: []
tags: • risc-v
• vector
• optimization
discussion_id_link: —
bugzilla_pr: —
url: https://github.com/gcc-mirror/gcc/commit/63fa52f94b89eefb8d56829d53bb8a59015f0bb6
date: 2026-09-02T00:00:00.000Z

This commit enables register overlap for the ‘undef’ form of the vwmaccu.vx dual-widen ternary VX instruction in the RISC-V vector extension. This change aligns the vwmaccu.vx instruction’s register handling with other similar instructions, ensuring consistency.