Landing: 71fe685aaadf
Project / Subsystem
gcc / risc-v
Date
2026-09-03
Author
Pan Li
Commit
71fe685aaadf6cfae13ec46a38fb76a26562823b
Source
github
Perf win
No
Breaking
No
All attributes
- project
- gcc
- subsystem
- risc-v
- patch_id
- —
- commit_hash
- 71fe685aaadf6cfae13ec46a38fb76a26562823b
- source_type
- github
- headline
- RISC-V: Add test cases for vwmaccu.vx undef undefined register overlap
- tldr
- New RISC-V test cases validate `vwmaccu.vx` undef instruction with undefined register overlap.
- author
- Pan Li
- outcome
- committed
- performance_win
- false
- breaking_change
- false
- series_id
- —
- series_parts
- []
- tags
-
- • risc-v
- • vector
- • testing
- discussion_id_link
- —
- bugzilla_pr
- —
- date
- 2026-09-03T00:00:00.000Z
This commit adds a comprehensive set of test cases to the RISC-V test suite. These tests specifically focus on the vwmaccu.vx instruction within the vector extension, verifying its behavior when register overlap is present and the instruction form is undefined.