Landing: a87ea5b3cfc0
Project / Subsystem
gcc / risc-v
Date
2026-09-03
Author
Pan Li
Commit
a87ea5b3cfc0a680c25865a83c1380ffb8bd72b2
Source
github
Perf win
No
Breaking
No
All attributes
- project
- gcc
- subsystem
- risc-v
- patch_id
- —
- commit_hash
- a87ea5b3cfc0a680c25865a83c1380ffb8bd72b2
- source_type
- github
- headline
- RISC-V: Add test cases for vwmaccu.vx undef register overlap
- tldr
- New test cases verify register overlap for vwmaccu.vx undef in RISC-V vector operations.
- author
- Pan Li
- outcome
- committed
- performance_win
- false
- breaking_change
- false
- series_id
- —
- series_parts
- []
- tags
-
- • risc-v
- • vector
- • testing
- discussion_id_link
- —
- bugzilla_pr
- —
- date
- 2026-09-03T00:00:00.000Z
This commit introduces several new test cases for the RISC-V vector extension, specifically targeting the vwmaccu.vx instruction with undefined register overlap. These tests ensure correct behavior when register groups overlap, which can occur during instruction combining.