Landing: 33097f255c60

← All landings

Project / Subsystem

gcc / aarch64

Date

2026-09-05

Author

Artemiy Volkov

Commit

33097f255c609674e20feb6c4ca6cd10e25ac801

Source

github

Perf win

No

Breaking

No

View on GitHub →

All attributes

project: gcc
subsystem: aarch64
patch_id: —
commit_hash: 33097f255c609674e20feb6c4ca6cd10e25ac801
source_type: github
headline: aarch64: Introduce and employ the extsize iterator for instruction suffixes
tldr: New 'extsize' iterator improves instruction pattern matching for aarch64 by distinguishing between extension and load/store suffixes.
author: Artemiy Volkov
outcome: committed
performance_win: false
breaking_change: false
series_id: —
series_parts: []
tags: • aarch64
• backend
• instruction-selection
discussion_id_link: —
bugzilla_pr: —
url: https://github.com/gcc-mirror/gcc/commit/33097f255c609674e20feb6c4ca6cd10e25ac801
date: 2026-09-05T00:00:00.000Z

The aarch64 backend has introduced a new extsize iterator to correctly represent instruction suffixes for 32-bit operations. Previously, the generic size iterator was used for both extension instructions (like uxtw) and load/store instructions, incorrectly expanding to ‘w’ for 32-bit modes in the latter case. The extsize iterator expands to ‘w’ for extensions but an empty string for loads/stores, resolving issues with instructions like ldrw or strw which do not exist. This change ensures accurate pattern matching for SIMD and general-purpose instructions that have distinct suffixes for extensions versus memory operations.