Landing: 42deb9a3bfe4
Project / Subsystem
gcc / risc-v
Date
2026-09-05
Author
Pan Li
Commit
42deb9a3bfe42d22412c416a82ccc713e84ed3d1
Source
github
Perf win
No
Breaking
No
All attributes
- project
- gcc
- subsystem
- risc-v
- patch_id
- —
- commit_hash
- 42deb9a3bfe42d22412c416a82ccc713e84ed3d1
- source_type
- github
- headline
- RISC-V: Add test cases for vwredsumu.vs register overlap
- tldr
- Adds test cases to verify correct register usage for RISC-V vwredsumu.vs instruction.
- author
- Pan Li
- outcome
- committed
- performance_win
- false
- breaking_change
- false
- series_id
- —
- series_parts
- []
- tags
-
- • risc-v
- • vector instructions
- • testing
- discussion_id_link
- —
- bugzilla_pr
- —
- date
- 2026-09-05T00:00:00.000Z
New test cases ensure that the scalar operand vs1 for the RISC-V widening reduction instruction vwredsumu.vs does not overlap with the vs2 register group. This addresses potential register allocation issues and maintains correct program execution.