Landing: 7e88b4e76418
Project / Subsystem
gcc / risc-v
Date
2026-09-05
Author
Jin Ma
Commit
7e88b4e76418b131268802ccba5f74cf1835fc66
Source
github
Perf win
No
Breaking
No
All attributes
- project
- gcc
- subsystem
- risc-v
- patch_id
- —
- commit_hash
- 7e88b4e76418b131268802ccba5f74cf1835fc66
- source_type
- github
- headline
- RISC-V vector crypto register allocation fixed.
- tldr
- Prevents register overlap issues in RISC-V vector crypto instructions.
- author
- Jin Ma
- outcome
- committed
- performance_win
- false
- breaking_change
- false
- series_id
- —
- series_parts
- []
- tags
-
- • risc-v
- • vector
- • crypto
- • register allocation
- discussion_id_link
- —
- bugzilla_pr
- —
- date
- 2026-09-05T00:00:00.000Z
This commit addresses register allocation conflicts for RISC-V vector crypto instructions, specifically for vsm3me.vv, vsm3c.vi, vaes*.vs, vsm4r.vs, vsha2ms.vv, vsha2ch.vv, and vsha2cl.vv. It introduces early-clobber destination constraints to prevent the destination register (vd) from overlapping with source registers (vs2 or vs1) where specified by the Vector Crypto extension.