Landing: efc69e28d8c5

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Project / Subsystem

gcc / xtensa

Date

2026-09-07

Author

Takayuki 'January June' Suwa

Commit

efc69e28d8c552a98f09a6c17cedaa189d7bce25

Source

github

Perf win

No

Breaking

No

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All attributes

project: gcc
subsystem: xtensa
patch_id: —
commit_hash: efc69e28d8c552a98f09a6c17cedaa189d7bce25
source_type: github
headline: xtensa: Discourage hardware FP registers for SFmode load/store
tldr: Xtensa backend prefers general-purpose registers over hardware FP registers for single-precision float loads/stores to reduce code size.
author: Takayuki 'January June' Suwa
outcome: committed
performance_win: false
breaking_change: false
series_id: —
series_parts: []
tags: • xtensa
• code-size
• optimization
discussion_id_link: —
bugzilla_pr: —
url: https://github.com/gcc-mirror/gcc/commit/efc69e28d8c552a98f09a6c17cedaa189d7bce25
date: 2026-09-07T00:00:00.000Z

This commit modifies the Xtensa backend to prefer general-purpose registers (GPRs) over hardware floating-point registers (FPRs) for single-precision floating-point (SFmode) load and store operations. While functionally equivalent, using GPRs results in smaller code size when the Code Density Option is enabled. This is achieved by prefixing the hardware FP register constraints in the MD insn definition with an asterisk (’*’), signaling a lower priority. The change is demonstrated with an example showing reduced instruction encoding length for loads, stores, and immediate assignments.