Landing: 1f3017b56321

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Project / Subsystem

gcc / risc-v

Date

2026-09-10

Author

Pan Li

Commit

1f3017b56321ee05a4ffd5615285045ba8816753

Source

github

Perf win

No

Breaking

No

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All attributes

project: gcc
subsystem: risc-v
patch_id: —
commit_hash: 1f3017b56321ee05a4ffd5615285045ba8816753
source_type: github
headline: RISC-V: Fix ICE for widening insn with equal LMUL
tldr: Resolves compiler internal error when RISC-V widening instructions have same source and destination register counts.
author: Pan Li
outcome: committed
performance_win: false
breaking_change: false
series_id: —
series_parts: []
tags: • risc-v
• vector
• compiler bug
discussion_id_link: —
bugzilla_pr: —
url: https://github.com/gcc-mirror/gcc/commit/1f3017b56321ee05a4ffd5615285045ba8816753
date: 2026-09-10T00:00:00.000Z

This commit fixes an internal compiler error (ICE) in the RISC-V backend related to widening vector instructions. The error occurred when the destination and source operands of a widening instruction used the same number of registers (nregs). The compiler’s riscv_v_widen_constraint_ok function had an incorrect assertion that nregs must be 1 in such cases. This patch modifies the function to return false instead of asserting when nregs is equal but greater than 1, preventing the ICE and allowing correct code generation for valid widening operations.