Landing: 3b4fd4a3b6e6
Project / Subsystem
gcc / gcc/risc-v
Date
2026-09-11
Author
Jeff Law
Commit
3b4fd4a3b6e633dd2d2af7d3234bb79ccb61e3c5
Source
github
Perf win
Yes
Breaking
No
All attributes
- project
- gcc
- subsystem
- gcc/risc-v
- patch_id
- —
- commit_hash
- 3b4fd4a3b6e633dd2d2af7d3234bb79ccb61e3c5
- source_type
- github
- headline
- Fix RISC-V ADDI+AND+CTZ optimization bugs
- tldr
- Corrects two flaws in an optimization that transforms sequences of ADDI, AND, and CTZ instructions on RISC-V.
- author
- Jeff Law
- outcome
- committed
- performance_win
- true
- breaking_change
- false
- series_id
- —
- series_parts
- []
- tags
-
- • risc-v
- • optimization
- • compiler bug
- discussion_id_link
- —
- bugzilla_pr
- —
- date
- 2026-09-11T00:00:00.000Z
This commit addresses two bugs in a RISC-V optimization that converts sequences of ADDI, AND, and CTZ (count trailing zeros) instructions into a more efficient CTZ followed by BCLR (bit clear). The first bug caused the original AND instruction to be incorrectly retained, leading to the clearing of two bits instead of one. The second bug was an off-by-one error in the safety check for moving the CTZ instruction, which could lead to incorrect transformations when the AND instruction modified a value used by CTZ. Both issues are now fixed, and a new test case is added.