Landing: 6924bcee14bd

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Project / Subsystem

gcc / risc-v

Date

2026-09-12

Author

Pan Li

Commit

6924bcee14bdcecf0fcb6764f546dd7ca8ca8f9a

Source

github

Perf win

Breaking

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All attributes

project: gcc
subsystem: risc-v
patch_id: —
commit_hash: 6924bcee14bdcecf0fcb6764f546dd7ca8ca8f9a
source_type: github
headline: RISC-V: Fix register overlap for vs1 of widening integer reduction
tldr: Ensures vs1 does not overlap vs2 in RISC-V widening reductions.
author: Pan Li
outcome: committed
performance_win: false
breaking_change: false
series_id: —
series_parts: []
tags: • risc-v
• vector instructions
• optimization
discussion_id_link: —
bugzilla_pr: —
url: https://github.com/gcc-mirror/gcc/commit/6924bcee14bdcecf0fcb6764f546dd7ca8ca8f9a
date: 2026-09-12T00:00:00.000Z

This change fixes a register overlap issue in RISC-V widening integer reductions where the vs1 operand could fall within the vs2 register group. A new constraint, Wn3, is introduced to enforce that vs1 does not overlap with vs2, adhering to the RISC-V vector specification and preventing incorrect instruction generation.