Landing: c26ada64060e
Project / Subsystem
gcc / risc-v
Date
2026-09-12
Author
Pan Li
Commit
c26ada64060ebe19995d1937ebfde5082f0a3442
Source
github
Perf win
No
Breaking
No
All attributes
- project
- gcc
- subsystem
- risc-v
- patch_id
- —
- commit_hash
- c26ada64060ebe19995d1937ebfde5082f0a3442
- source_type
- github
- headline
- RISC-V: Add test cases for vwredsum.vs register overlap
- tldr
- Adds tests to ensure no register overlap for RISC-V vwredsum.vs.
- author
- Pan Li
- outcome
- committed
- performance_win
- false
- breaking_change
- false
- series_id
- —
- series_parts
- []
- tags
-
- • risc-v
- • vector instructions
- • testing
- discussion_id_link
- —
- bugzilla_pr
- —
- date
- 2026-09-12T00:00:00.000Z
This commit introduces new test cases to verify that the vs1 register in the RISC-V vwredsum.vs instruction does not overlap with the vs2 register group. This helps prevent incorrect register usage and ensures the correct interpretation of operands.