Landing: f408d09eedfa

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Project / Subsystem

gcc / xtensa

Date

2026-09-12

Author

Takayuki 'January June' Suwa

Commit

f408d09eedfad5c9b470750c85444faea7f7ccc7

Source

github

Perf win

Breaking

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All attributes

project: gcc
subsystem: xtensa
patch_id: —
commit_hash: f408d09eedfad5c9b470750c85444faea7f7ccc7
source_type: github
headline: XTENSA: Revise REGNO_REG_CLASS macro for minimal register class mapping
tldr: Xtensa target now correctly maps register numbers to their minimal encompassing register class.
author: Takayuki 'January June' Suwa
outcome: committed
performance_win: false
breaking_change: false
series_id: —
series_parts: []
tags: • xtensa
• register allocation
• compiler internals
discussion_id_link: —
bugzilla_pr: —
url: https://github.com/gcc-mirror/gcc/commit/f408d09eedfad5c9b470750c85444faea7f7ccc7
date: 2026-09-12T00:00:00.000Z

The REGNO_REG_CLASS macro for the Xtensa target has been revised to accurately map each hardware register number to its minimal register class. This is achieved by generating a mapping within xtensa_conditional_register_usage that references a new global array, xtensa_regno_to_class. This ensures that the compiler always selects the most specific register class for a given register, as recommended by GCC’s internal documentation.