Landing: 03e14ea7c5f2

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Project / Subsystem

gcc / risc-v

Date

2026-09-13

Author

Jeff Law

Commit

03e14ea7c5f2f906a702636a5190f3a2f92021eb

Source

github

Perf win

No

Breaking

No

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All attributes

project: gcc
subsystem: risc-v
patch_id: —
commit_hash: 03e14ea7c5f2f906a702636a5190f3a2f92021eb
source_type: github
headline: Removes RV64 optimization for bit clearing, simplifying code.
tldr: Removes a complex optimization for variable bit clearing on RISC-V RV64 due to correctness issues, simplifying the compiler's output.
author: Jeff Law
outcome: committed
performance_win: false
breaking_change: false
series_id: —
series_parts: []
tags: • risc-v
• optimization
• compiler
discussion_id_link: —
bugzilla_pr: —
url: https://github.com/gcc-mirror/gcc/commit/03e14ea7c5f2f906a702636a5190f3a2f92021eb
date: 2026-09-13T00:00:00.000Z

This commit removes an optimization pass on RISC-V RV64 that aimed to replace sequences like addi+and with ctz+bclr for bit clearing operations. The optimization, intended to reduce instruction count, incorrectly handled 32-bit operations on 64-bit registers and produced incorrect sign extensions in some cases. By removing the problematic part of the pass, the compiler now correctly rejects this optimization when it cannot be safely applied, improving correctness for 32-bit operations on RV64.