Landing: f311d59c4d45

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Project / Subsystem

gcc / ira

Date

2026-09-16

Author

Stefan Schulze Frielinghaus

Commit

f311d59c4d45f5042029647c88966e2e48330adf

Source

github

Perf win

No

Breaking

No

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All attributes

project: gcc
subsystem: ira
patch_id: —
commit_hash: f311d59c4d45f5042029647c88966e2e48330adf
source_type: github
headline: IRA: Treat hard register constraints like single register class constraints
tldr: Instruction Recognition and Allocation treats hard register constraints more consistently with register class constraints.
author: Stefan Schulze Frielinghaus
outcome: committed
performance_win: false
breaking_change: false
series_id: —
series_parts: []
tags: • ira
• optimization
• register allocation
discussion_id_link: —
bugzilla_pr: —
url: https://github.com/gcc-mirror/gcc/commit/f311d59c4d45f5042029647c88966e2e48330adf
date: 2026-09-16T00:00:00.000Z

The Instruction Recognition and Allocation (IRA) pass now treats hard register constraints identically to constraints for single register classes. This change standardizes how operand constraints are processed, ensuring that register numbers are correctly computed for both types of constraints. The update simplifies logic within the process_single_reg_class_operands function and renames related helper functions for clarity. Some test cases were adjusted to account for potential changes in instruction selection and register allocation.