Landing: 4a2a0a4360fa

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Project / Subsystem

gcc / risc-v

Date

2026-09-18

Author

Michiel Derhaeg

Commit

4a2a0a4360fa37a30b8c00a29095ad9fdb63c2f3

Source

github

Perf win

Yes

Breaking

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All attributes

project: gcc
subsystem: risc-v
patch_id: —
commit_hash: 4a2a0a4360fa37a30b8c00a29095ad9fdb63c2f3
source_type: github
headline: RISC-V: Avoid emitting shNadd with a virtual register base
tldr: RISC-V code generation avoids shNadd instruction with virtual register bases to enable better frame offset folding.
author: Michiel Derhaeg
outcome: committed
performance_win: true
breaking_change: false
series_id: —
series_parts: []
tags: • risc-v
• code-generation
• optimization
discussion_id_link: —
bugzilla_pr: —
url: https://github.com/gcc-mirror/gcc/commit/4a2a0a4360fa37a30b8c00a29095ad9fdb63c2f3
date: 2026-09-18T00:00:00.000Z

The RISC-V code generator now avoids emitting the shNadd instruction when its base register is a virtual register. This prevents the frame offset from being folded into the instruction later, which previously resulted in longer instruction sequences. The change simplifies generated code for certain stack access patterns.