Landing: ca5e88d7531a
Project / Subsystem
gcc / risc-v
Date
2026-09-18
Author
Pan Li
Commit
ca5e88d7531aa673a937007a0e21a141eee743e9
Source
github
Perf win
No
Breaking
No
All attributes
- project
- gcc
- subsystem
- risc-v
- patch_id
- —
- commit_hash
- ca5e88d7531aa673a937007a0e21a141eee743e9
- source_type
- github
- headline
- RISC-V: Allow RVV register overlap for vfwadd.wv
- tldr
- Compiler now permits specific register overlap scenarios for the RISC-V vector `vfwadd.wv` instruction.
- author
- Pan Li
- outcome
- committed
- performance_win
- false
- breaking_change
- false
- series_id
- —
- series_parts
- []
- tags
-
- • risc-v
- • compiler
- • vector
- • optimization
- discussion_id_link
- —
- bugzilla_pr
- —
- date
- 2026-09-18T00:00:00.000Z
This commit adjusts constraints for the RISC-V vector vfwadd.wv instruction to allow certain register overlaps. Previously, the instruction had strict constraints regarding operand register overlap. New constraints (Wn4 and Wvr) are introduced and applied to operands vs1 and vs2 respectively, enabling cases where the narrow operand vs1 might fall within the vs2 register group, provided it doesn’t overlap the entire vs2 group.