Landing: 0de4790181fc
Project / Subsystem
gcc / risc-v
Date
2026-09-21
Author
Michiel Derhaeg
Commit
0de4790181fcf74665c3c27e901559a16d3e4991
Source
github
Perf win
Yes
Breaking
No
All attributes
- project
- gcc
- subsystem
- risc-v
- patch_id
- —
- commit_hash
- 0de4790181fcf74665c3c27e901559a16d3e4991
- source_type
- github
- headline
- RISC-V: ARC-V RMX-100 load latency updated.
- tldr
- Updates load instruction latency for the ARC-V RMX-100 core.
- author
- Michiel Derhaeg
- outcome
- committed
- performance_win
- true
- breaking_change
- false
- series_id
- —
- series_parts
- []
- tags
-
- • risc-v
- • performance
- • latency
- discussion_id_link
- —
- bugzilla_pr
- —
- date
- 2026-09-21T00:00:00.000Z
The load instruction latency for the ARC-V RMX-100 processor has been updated. The previous latency value was considered a worst-case scenario, and the new value better reflects the likely case, potentially improving scheduling and performance. Additionally, the commit merges floating-point load instructions with general loads and updates branding information.