Landing: 440ade62c966

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Project / Subsystem

gcc / risc-v

Date

2026-09-21

Author

Ancheng.Qiao

Commit

440ade62c96692a25c4b0d68bd47f1c04d6834fb

Source

github

Perf win

No

Breaking

No

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All attributes

project: gcc
subsystem: risc-v
patch_id: —
commit_hash: 440ade62c96692a25c4b0d68bd47f1c04d6834fb
source_type: github
headline: RISC-V: Fix FPR saves below SP with Zcmp
tldr: RISC-V code generation for Zcmp extension avoids corrupted callee-saved FPRs on interrupt.
author: Ancheng.Qiao
outcome: committed
performance_win: false
breaking_change: false
series_id: —
series_parts: []
tags: • risc-v
• optimization
• abi
discussion_id_link: —
bugzilla_pr: —
url: https://github.com/gcc-mirror/gcc/commit/440ade62c96692a25c4b0d68bd47f1c04d6834fb
date: 2026-09-21T00:00:00.000Z

This change corrects how callee-saved floating-point registers (FPRs) are saved on the stack when using the RISC-V Zcmp extension and optimizing for size (-Os). Previously, the prologue could incorrectly calculate the space needed for these registers, leading to them being stored below the stack pointer without sufficient allocation. This could cause an interrupt to overwrite these registers before they were properly saved, corrupting program state. The fix ensures that only as many FPRs are folded into the cm.push reserve as can be physically stored.