Landing: 611705766efc
Project / Subsystem
gcc / risc-v
Date
2026-09-21
Author
Pan Li
Commit
611705766efc7ea1dc2fa01e344db20e06546a27
Source
github
Perf win
No
Breaking
No
All attributes
- project
- gcc
- subsystem
- risc-v
- patch_id
- —
- commit_hash
- 611705766efc7ea1dc2fa01e344db20e06546a27
- source_type
- github
- headline
- RISC-V: Fix ICE for widening instructions with disparate register counts
- tldr
- Compiler no longer crashes when RISC-V widening instructions involve source and destination registers with different counts.
- author
- Pan Li
- outcome
- committed
- performance_win
- false
- breaking_change
- false
- series_id
- —
- series_parts
- []
- tags
-
- • risc-v
- • compiler
- • optimization
- • vector
- discussion_id_link
- —
- bugzilla_pr
- —
- date
- 2026-09-21T00:00:00.000Z
The compiler previously asserted that destination register counts must exceed source register counts for widening instructions in RISC-V. This commit modifies the riscv_v_widen_constraint_ok function to return false instead of asserting when the destination has fewer registers than the source. This resolves an internal compiler error (ICE) that occurred in specific scenarios, such as when widening a vector register group.