Landing: 2e8bb62f9858
Project / Subsystem
gcc / risc-v
Date
2026-09-22
Author
Pan Li
Commit
2e8bb62f985815704390963e083276226be15939
Source
github
Perf win
Yes
Breaking
No
All attributes
- project
- gcc
- subsystem
- risc-v
- patch_id
- —
- commit_hash
- 2e8bb62f985815704390963e083276226be15939
- source_type
- github
- headline
- RISC-V: Allow register overlap for widened float vector instructions
- tldr
- RISC-V vector instructions now allow register overlap for widened float operations.
- author
- Pan Li
- outcome
- committed
- performance_win
- true
- breaking_change
- false
- series_id
- —
- series_parts
- []
- tags
-
- • risc-v
- • vector
- • optimization
- • compiler
- discussion_id_link
- —
- bugzilla_pr
- —
- date
- 2026-09-22T00:00:00.000Z
The RISC-V vector extension (RVV) now permits register overlap for dual-widening floating-point instructions, including vfwadd.vv, vfwsub.vv, and vfwmul.vv. This change is accompanied by new test cases in the testsuite to verify correct handling of register group overlaps for various floating-point types and vector mask configurations.