Landing: 6e82949c656b

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Project / Subsystem

gcc / risc-v

Date

2026-09-22

Author

Pan Li

Commit

6e82949c656b32424e50123a48bdcd018200b401

Source

github

Perf win

Breaking

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All attributes

project: gcc
subsystem: risc-v
patch_id: —
commit_hash: 6e82949c656b32424e50123a48bdcd018200b401
source_type: github
headline: RISC-V: Add tests for vfwmul.vv register overlap
tldr: New test cases verify register overlap handling for RISC-V vfwmul.vv vector instructions.
author: Pan Li
outcome: committed
performance_win: false
breaking_change: false
series_id: —
series_parts: []
tags: • risc-v
• vector
• testing
discussion_id_link: —
bugzilla_pr: —
url: https://github.com/gcc-mirror/gcc/commit/6e82949c656b32424e50123a48bdcd018200b401
date: 2026-09-22T00:00:00.000Z

This commit introduces a suite of new test cases to the RISC-V testsuite, specifically targeting the vfwmul.vv vector instruction. These tests focus on scenarios involving register group overlap with various floating-point formats (f16, f32) and vector mask configurations, ensuring the compiler correctly handles these operations.