Landing: f8c83fa5bce8

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Project / Subsystem

gcc / risc-v

Date

2026-09-22

Author

Pan Li

Commit

f8c83fa5bce8da5790286e7982a546d711ea37b0

Source

github

Perf win

Breaking

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All attributes

project: gcc
subsystem: risc-v
patch_id: —
commit_hash: f8c83fa5bce8da5790286e7982a546d711ea37b0
source_type: github
headline: RISC-V: Add tests for vfwsub.vv register overlap
tldr: New test cases verify register overlap handling for RISC-V vfwsub.vv vector instructions.
author: Pan Li
outcome: committed
performance_win: false
breaking_change: false
series_id: —
series_parts: []
tags: • risc-v
• vector
• testing
discussion_id_link: —
bugzilla_pr: —
url: https://github.com/gcc-mirror/gcc/commit/f8c83fa5bce8da5790286e7982a546d711ea37b0
date: 2026-09-22T00:00:00.000Z

This commit adds a new set of test cases to the RISC-V testsuite, focusing on the vfwsub.vv vector instruction. The tests examine scenarios with register group overlap, using various floating-point types (f16, f32) and vector mask configurations to ensure the compiler’s correct implementation.