Landing: 5d2597a0b61d
Project / Subsystem
gcc / risc-v
Date
2026-09-28
Author
Pan Li
Commit
5d2597a0b61da3c48c2f9dd3768c9806c980bbf8
Source
github
Perf win
No
Breaking
No
All attributes
- project
- gcc
- subsystem
- risc-v
- patch_id
- —
- commit_hash
- 5d2597a0b61da3c48c2f9dd3768c9806c980bbf8
- source_type
- github
- headline
- RISC-V: Add test cases for vfwsub.vf reg overlap
- tldr
- Adds new RISC-V vector test cases for register group overlap with vfwsub.vf instructions.
- author
- Pan Li
- outcome
- committed
- performance_win
- false
- breaking_change
- false
- series_id
- —
- series_parts
- []
- tags
-
- • risc-v
- • vector
- • testing
- • rvv
- • optimization
- discussion_id_link
- —
- bugzilla_pr
- —
- date
- 2026-09-28T00:00:00.000Z
This commit introduces a set of new test cases for the RISC-V Vector (RVV) extension, focusing on register group overlap when using the vfwsub.vf instruction. These tests, covering various data types (f16, f32) and vector lengths (m1, m2, m4, mf2, mf4), aim to ensure the compiler correctly handles register allocation for wide floating-point subtraction operations.