Landing: a3f5541bcf62
Project / Subsystem
gcc / risc-v
Date
2026-09-28
Author
Pan Li
Commit
a3f5541bcf62d1142cea7f7f70afcabf888d947c
Source
github
Perf win
Yes
Breaking
No
All attributes
- project
- gcc
- subsystem
- risc-v
- patch_id
- —
- commit_hash
- a3f5541bcf62d1142cea7f7f70afcabf888d947c
- source_type
- github
- headline
- RISC-V: Allow RVV register overlap for vfw{add,sub,mul}.vf
- tldr
- RISC-V compiler now permits register overlap for wide floating-point vector instructions.
- author
- Pan Li
- outcome
- committed
- performance_win
- true
- breaking_change
- false
- series_id
- —
- series_parts
- []
- tags
-
- • risc-v
- • vector
- • optimization
- • rvv
- discussion_id_link
- —
- bugzilla_pr
- —
- date
- 2026-09-28T00:00:00.000Z
The RISC-V GCC backend now allows register group overlap for wide floating-point vector instructions, specifically vfwadd.vf, vfwsub.vf, and vfwmul.vf. This change aligns the handling of these instructions with their vector-vector counterparts (.vv) and leverages the Wvr constraint in the vector.md file, potentially enabling more efficient instruction scheduling.