Landing: ba20ee9a2cd5
Project / Subsystem
gcc / risc-v
Date
2026-09-28
Author
Pan Li
Commit
ba20ee9a2cd5791cf571c873dbf331cdfbe6181d
Source
github
Perf win
No
Breaking
No
All attributes
- project
- gcc
- subsystem
- risc-v
- patch_id
- —
- commit_hash
- ba20ee9a2cd5791cf571c873dbf331cdfbe6181d
- source_type
- github
- headline
- RISC-V: Add test cases for vfwmul.vf reg overlap
- tldr
- Adds new RISC-V vector test cases for register group overlap with vfwmul.vf instructions.
- author
- Pan Li
- outcome
- committed
- performance_win
- false
- breaking_change
- false
- series_id
- —
- series_parts
- []
- tags
-
- • risc-v
- • vector
- • testing
- • rvv
- • optimization
- discussion_id_link
- —
- bugzilla_pr
- —
- date
- 2026-09-28T00:00:00.000Z
This commit introduces a suite of new test cases for the RISC-V Vector (RVV) extension, specifically targeting register group overlap scenarios for the vfwmul.vf instruction. The tests cover various data types (f16, f32) and vector lengths (m1, m2, m4, mf2, mf4), ensuring correct handling of register resources during wide floating-point multiplication operations.