Landing: ec09d7005033

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Project / Subsystem

gcc / risc-v

Date

2026-09-28

Author

Naveen

Commit

ec09d7005033eb1f28304af80d888b81bb3063c7

Source

github

Perf win

Yes

Breaking

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All attributes

project: gcc
subsystem: risc-v
patch_id: —
commit_hash: ec09d7005033eb1f28304af80d888b81bb3063c7
source_type: github
headline: RISC-V: Add conditional negate expansion
tldr: RISC-V gets a new instruction expansion for conditional negation of integral values.
author: Naveen
outcome: committed
performance_win: true
breaking_change: false
series_id: —
series_parts: []
tags: • risc-v
• optimization
• instruction expansion
discussion_id_link: —
bugzilla_pr: —
url: https://github.com/gcc-mirror/gcc/commit/ec09d7005033eb1f28304af80d888b81bb3063c7
date: 2026-09-28T00:00:00.000Z

A new expansion, negcc, has been added for integral comparisons on RISC-V architectures. This expansion implements the pattern ‘X ? -X : X’ using a sequence of compare, mask, XOR, and add operations. The new pseudo instruction helps existing if-conversion paths by providing a distinct output pseudo for the XOR result, ensuring it’s assigned only once. This change enables more efficient conditional negation for integral types on RISC-V.