Landing: 8802cd9fdbef
Project / Subsystem
gcc / xtensa
Date
2026-10-04
Author
Takayuki 'January June' Suwa
Commit
8802cd9fdbefee623761dbddf93f80685ac53f7b
Source
github
Perf win
No
Breaking
No
All attributes
- project
- gcc
- subsystem
- xtensa
- patch_id
- —
- commit_hash
- 8802cd9fdbefee623761dbddf93f80685ac53f7b
- source_type
- github
- headline
- Refurbish xtensa 'adddi3' MD pattern for 64-bit addition
- tldr
- Improves xtensa's 64-bit addition pattern by handling carry propagation correctly.
- author
- Takayuki 'January June' Suwa
- outcome
- committed
- performance_win
- false
- breaking_change
- false
- series_id
- —
- series_parts
- []
- tags
-
- • xtensa
- • optimization
- • 64-bit
- • instruction selection
- discussion_id_link
- —
- bugzilla_pr
- —
- date
- 2026-10-04T00:00:00.000Z
This commit refactors the adddi3 Machine Description (MD) pattern for Xtensa to correctly handle 64-bit integer addition on 32-bit architectures. The original pattern struggled with carry propagation when the same register was used for operands and results. The updated pattern utilizes RTL instruction combination to perform the addition and carry check in parallel, resolving potential issues with intermediate assignments and ensuring correctness.