RISC-V: Add experimental support for Zvabd extension
The RISC-V Zvabd extension is ready; the author asks for the binutils patch to land so the GCC patch isn't blocked.
Chen Zhongyao notes that the RISC-V Zvabd extension is now in the “Freeze” state and asks Jiawei to pick up the binutils patch. The corresponding GCC patch is ready but blocked, pending the binutils changes.
- maintainer
Agrees to pick up the patch and update it based on the current specification.
“Sure, I can help pick this up. Thanks for the updated status and spec links. Since Zvabd is now in Freeze and the only remaining change appears to be the mnemonic rename, I will refresh my earlier binutils patch and update it against the current spec.”
In Details
This thread discusses adding support for the RISC-V Zvabd extension to binutils. The Zvabd extension adds instructions for vector absolute difference operations. Binutils support is necessary for assemblers and linkers to handle the new instructions. GCC support depends on binutils support.
For Context
This discussion concerns adding support for a new set of instructions (the Zvabd extension) to the RISC-V architecture. The binutils project provides tools like assemblers and linkers that translate human-readable code into machine code. For the compiler (GCC) to use these new instructions, binutils needs to understand them first.