RISC-V: Add experimental support for Zvabd extension
Jiawei will update the binutils patch for the Zvabd extension, which is now in Freeze, after renaming the mnemonic.
Jiawei is picking up Zhongyao’s work to add experimental support for the RISC-V Zvabd extension in binutils. The Zvabd extension specification is now in Freeze, and the only remaining change is a mnemonic rename. Jiawei will refresh the binutils patch and update it against the current specification, including opcodes, gas changes, and tests.
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Thanks Jiawei for picking this up.
“Thanks a ton!”
In Details
The RISC-V Zvabd extension adds instructions for dealing with bfloat16 floating-point numbers. This patch series updates binutils to support the new instructions and mnemonics. The patch will primarily affect opcodes/riscv-opc.c and the gas assembler.
For Context
The RISC-V architecture is modular, allowing for various extensions to be added to the base instruction set. These extensions provide additional functionality, such as specialized instructions for floating-point arithmetic or cryptography. Supporting these extensions in binutils (the GNU assembler, linker, and related tools) involves updating the assembler to recognize the new instructions and generate the appropriate machine code. This allows developers to use the new instructions in their programs.