Support AVX10_V2_AUX instructions
Jan Beulich states he is working on a patch to separate AVX10.1-aux from AVX10.2.
Jan Beulich responds to a question about supporting a specific CPUID bit related to AVX10 instructions. He informs the thread that he is developing a patch to separate the AVX10.1 preliminary auxiliary instructions from the AVX10.2 set, indicating they will be available under a new CPUID bit. This is in response to a query about the plan for supporting that bit.
- reviewer
States that he is working on a patch to distinguish AVX10.1 auxiliary instructions from AVX10.2, which will be available under a new CPUID bit.
“Just to mention that I have a patch in the works to separate 10.1-aux from 10.2.”
In Details
This brief exchange appears to be a follow-up to a patch series introducing AVX10_V2_AUX instructions. The context is the Intel/AMD CPUID mechanism used to enumerate supported instruction set extensions. The query 'What is your plan on supporting that bit?' likely refers to a CPUID bit associated with AVX10_V1_AUX or a related feature. Jan Beulich's response indicates he is preparing a patch to refine the support for these AVX10 variants, specifically isolating AVX10.1-aux from AVX10.2 and enabling it via a distinct CPUID bit.
- AVX10_V2_AUX
- A set of auxiliary instructions related to the AVX10 instruction set extension, characterized by version 2.
- CPUID
- An x86 instruction that provides information about the processor's capabilities and features, including supported instruction sets. Processors use specific bits to indicate support for various extensions.
- AVX10.1
- An instruction set extension for x86 processors, representing an early version of AVX10 features.
- AVX10.2
- A later version of the AVX10 instruction set extension, potentially including more features or refinements over AVX10.1.
- instruction set extension
- An addition to a processor's base instruction set, providing new capabilities such as advanced vector operations (e.g., AVX).