RISC-V: EEW64 checking
Discussion on correct handling of RISC-V Zve64x extension checks in assembler and disassembler.
This discussion addresses the correct implementation of checks for the RISC-V Zve64x extension in binutils’ assembler and disassembler. Jan Beulich points out that the disassembler should also use the INSN_V_EEW64 flag and questions the redundancy of Zve32x checks. Nelson Chu agrees with this, suggesting that a new INSN_CLASS_ZVE64X would be a more appropriate way to handle these checks, aligning with the assembler’s logic and simplifying the code.
- proposer
Agrees with simplifying checks and suggests using `INSN_CLASS_ZVE64X` as a better approach.
“make sense. I forgot, probably just because people argued they want to dis-assembler old objects for segment load/store with EEW64 but without zve64x since this check may be added later that, but it doesn't matter now. I think using a new INSN_CLASS_ZVE64X should be the right way to go.”
- reviewer
Suggests that the disassembler should also use the INSN_V_EEW64 flag and that Zve32x checks are redundant. Questions the use of a flag when a new instruction class could be used.
“Like the assembler, the disassembler should also use the INSN_V_EEW64 flag. Respectively marked insns shouldn't be disassembled normally when Zve64x isn't enabled. While there also drop the redundant Zve32x check from gas: All affected insns are INSN_CLASS_V, which means Zve32x was already checked to be enabled (both V and Zve64x imply Zve32x). Question is why a flag was used in the first place…”
Technical Tradeoffs
- Simplifies checks by introducing a new instruction class, potentially improving maintainability.
In Details
This thread discusses refining the handling of RISC-V vector extension (V) checks in binutils. Jan Beulich proposes that the disassembler should align with the assembler by using the INSN_V_EEW64 flag and eliminate redundant checks for Zve32x. Nelson Chu agrees, suggesting a new INSN_CLASS_ZVE64X would be a cleaner approach for distinguishing instructions requiring the Zve64x extension, especially for segment load/store operations.
- RISC-V
- An open-source Instruction Set Architecture (ISA) that is modular and extensible.
- Zve64x
- A RISC-V extension that provides 64-bit vector processing capabilities.
- Zve32x
- A RISC-V extension that provides 32-bit vector processing capabilities.
- EEW64
- Element Extended Width 64. Refers to scalar data types with 64-bit width within RISC-V vector operations.
- Assembler
- A program that translates assembly language into machine code.
- Disassembler
- A program that translates machine code back into assembly language.
- INSN_V_EEW64
- A flag or indicator used in binutils to denote instructions related to 64-bit element width in vector operations.
- INSN_CLASS_V
- A classification used in binutils for instructions belonging to the RISC-V vector extension.