MIPS opcodes: fix transposed FS and FT in vadda and vmsuba
Fixes a bug in MIPS opcodes where the order of source operands FS and FT was transposed in vadda and vmsuba instructions.
A patch addresses a bug in the MIPS opcode definitions within opcodes/mips-opc.c where the source operands FS and FT were transposed in the vadda and vmsuba instructions. This transposition causes incorrect results in some cases because the PS2 multiplier is not symmetric and the order matters for the Booth recoder, leading to a one ULP difference.
- proposer
Submits a patch to correct the order of FS and FT operands in MIPS VLIW instructions vadda and vmsuba, explaining the impact on calculation correctness.
“Of the 36 three-operand ACC-destination VU0 macro-mode entries in `opcodes/mips-opc.c`, all but two list FS before FT. The two exceptions are vadda and vmsuba. For `vmsuba` this reversal silently changes results. The PS2 multiplier is not symmetric in its two source fields: the Booth recoder consumes FT while FS is shifted, so `vf[fs] * vf[ft]` and `vf[ft] * vf[fs]` differ by one ULP.”
In Details
This patch corrects a subtle but significant bug in the MIPS opcode definitions used by the binutils disassembler and possibly emulator/assembler. The vadda and vmsuba instructions, part of the MIPS VLIW (Very Long Instruction Word) extensions for the PS2, incorrectly implemented the order of their two floating-point source operands (FS and FT). This resulted in incorrect calculations due to the asymmetric nature of the underlying Booth recoder used in the multiplication step.
- MIPS
- Microprocessor without Interlocked Pipeline Stages. A RISC instruction set architecture widely used in embedded systems and formerly popular in workstations and servers.
- opcodes
- Operation codes. The part of a machine language instruction that specifies the operation to be performed.
- vadda
- A MIPS VLIW (Very Long Instruction Word) instruction likely related to vector addition of floating-point values, utilizing multiple source registers.
- vmsuba
- A MIPS VLIW (Very Long Instruction Word) instruction likely related to vector subtraction and addition, involving multiple source and destination registers.
- FS, FT
- Source registers 'FS' and 'FT' in MIPS VLIW instructions, specifying operands for arithmetic or vector operations.
- ULP
- Unit in the Last Place. The smallest possible difference between two floating-point numbers. A difference of one ULP indicates a minimal error in floating-point computation.
- Booth recoder
- An algorithm used in hardware for fast multiplication, particularly of signed two's complement numbers. Its asymmetry means operand order can affect results.