x86 AMX/ACE with >8 tiles
Discusses documentation and implementation considerations for x86 AMX/ACE supporting more than 8 tiles.
Christian Ludloff is seeking to document and discuss the behavior of x86 AMX/ACE implementations that support 16 or 32 tiles. The focus is on how existing hardware and instruction encodings (VEX, EVEX) can accommodate these larger tile configurations, and the implications for software. The discussion touches upon CPUID reporting, TILECFG modifications, and potential oversights in the AMX specification regarding memory operand width.
- proposer
Initiates discussion on documenting and supporting x86 AMX/ACE with more than 8 tiles, highlighting that existing VEX/EVEX encodings and TILECFG are mostly sufficient.
“I have been asked to document x86 AMX/ACE behavior of 16-tile and 32-tile implementations. The goal of a 16-tile or 32-tile HW implementation is to achieve extra performance by running SW that takes advantage of the extra tiles. In particular, said SW is expected to mostly run compute kernels, minimize process switches, and avoid tile usage in interrupt handlers for storage and networking. The…”
In Details
This discussion concerns the binutils assembler and disassembler's support for extended x86 AMX (Advanced Matrix Extensions) and ACE (Advanced Cryptography Extensions) instructions, specifically when implementations go beyond the initial 8 tiles. It delves into the microarchitectural details and instruction encoding implications, such as the use of VEX/EVEX prefixes and the TILECFG MSR, to support up to 16 or 32 tiles (TMMs). The thread also anticipates potential issues with the LDTILECFG/STTILECFG instruction's memory operand width.
- AMX
- Advanced Matrix Extensions, an x86 instruction set extension introduced with Intel's Ice Lake processors, designed to accelerate matrix operations, particularly for AI and machine learning workloads.
- ACE
- Advanced Cryptography Extensions, another x86 instruction set extension often associated with AMX, providing hardware acceleration for cryptographic operations.
- Tiles
- In the context of AMX, tiles are a fundamental unit of data processing, typically a 2D array used for matrix computations. Architectures can support a varying number of these tiles.
- VEX/EVEX
- Vector Extension (VEX) and Enhanced Vector Extension (EVEX) are prefixes for x86 instructions that allow for advanced vector processing, including broader register access and extended instruction set support like AMX.
- TILECFG
- Tile Configuration, a model-specific register (MSR) or similar mechanism used to configure the layout and dimensions of tiles used by AMX instructions.
- MSR
- Model-Specific Register, special registers used by the CPU to control its behavior or report status.
- CPUID
- An x86 instruction that returns information about the CPU's capabilities and features.