x86 WBINVD instruction prefix usage
Discussion on the correct allocation and usage of prefixes for the x86 WBINVD instruction, especially with new 'skip hints'.
Christian Ludloff brings attention to the usage of prefixes with the x86 WBINVD instruction, noting that new ‘skip hints’ (0x67, 0x66, 0xF3, 0xF2, and implementation-specific prefixes) are in active use by a corporate entity. The discussion clarifies that these prefixes modify the cache behavior of WBINVD without introducing new CPUID flags. The goal is to ensure binutils correctly handles these prefixes as they are being adopted.
- proposer
Raises concerns about the allocation and usage of prefixes for the x86 WBINVD instruction, particularly new 'skip hints'.
“If the use of x86 prefixes on WBINVD is not of your concern, you can stop reading. -------------------- 8< ------------------- I was asked to relay this to binutils/LKML. The new hints are in active use by a corporate entity other than Intel/AMD; therefore they shouldn't be redefined. 0x67 = no CODE hint => skip L0i/L1i cache 0x66 = no DATA hint => skip L0d/L1d cache 0xF3 = no INVD hint => skip i…”
In Details
This discussion concerns the x86 architecture's WBINVD instruction and the interpretation of its prefixes. Historically, WBINVD (opcode 0x0F, 0x09) invalidates caches. The WBNOINVD variant (with 0xF3 prefix) skips invalidations. New prefixes are being introduced (e.g., 0x67, 0x66, 0xF2, and segment register prefixes 0x26, 0x2E, etc.) that provide finer-grained control over which caches (code, data, LLC) are affected or allow implementation-specific behaviors. These prefixes are reportedly in active use, prompting a discussion on ensuring the assembler (as) and linker (`l…
- WBINVD
- An x86 instruction that writes back and invalidates the processor's on-chip caches.
- Prefix bytes
- In x86 assembly, bytes that precede an instruction opcode to modify its behavior, such as segment overrides, LOCK, or operation size.
- CPUID flag
- A flag returned by the CPUID instruction, used to query processor information, including supported features and capabilities.
- LLC
- Last-Level Cache. The cache closest to the processor cores that is shared among them, typically L3 cache.