x86 evolution: segmentation and paging removal
Proposal to drop x86 segmentation and compatibility modes for a new PM64-only world.
This discussion proposes a significant shift in x86 architecture support within binutils, aiming to remove legacy segmentation and compatibility modes. The changes are motivated by the advent of Intel’s FRED and APX specifications, and a new “PM64-only” operating mode. The proposal details the removal of numerous segment registers, table registers, and associated instructions, effectively simplifying the x86 architecture for future processors.
In Details
This proposal targets the removal of legacy x86 segmentation and compatibility modes, including segment registers (CS, SS, DS, ES, FS, GS), descriptor tables (GDT, IDT, LDT, TSS), and related instructions. This is driven by new architectural features like FRED (Flexible Return and Event Delivery) and APX, enabling a cleaner, "PM64-only" execution environment. The changes aim to simplify the assembler's and linker's handling of x86 code generation.