RISC-V: Describe relax passes with a pass table
A patch refactors the RISC-V relax pass mechanism by introducing a pass table, improving maintainability and paving the way for new relax passes.
Kito Cheng announces that a patch has been pushed, refactoring the RISC-V relax pass mechanism in binutils. The change introduces a pass table to describe each relax pass, which includes a reloc selector and optional hooks. This structure is intended to simplify the addition of new relax passes, such as vendor-specific ones or those for the Zcmt extension, by avoiding repetitive code for each new pass.
- proposer
Announces that the patch refactoring RISC-V relax passes has been pushed.
“pushed :)”
- proposer
Explains that the patch introduces a pass table to describe relax passes, simplifying the addition of new passes and improving the structure.
“_bfd_riscv_relax_section picks the relax function for each reloc with a chain of branches on info->relax_pass, and ld hard-codes the number of passes. Adding a pass means adding another branch and bumping the count in the emulation. This is a refactor to make room for more relax passes, such as vendor specific ones or one for Zcmt table jump. Each such pass would otherwise add its own branch, it…”
Technical Tradeoffs
- Increased complexity in the linker script due to the pass table structure.
- Potential for new bugs during the introduction of the pass table mechanism.
In Details
This patch refactors the relax pass mechanism in the RISC-V backend of binutils. Previously, adding new relax passes involved modifying a chain of branches and updating a hardcoded pass count. This change introduces a structured pass table (using struct riscv_relax_pass) that describes each pass with its selector, hooks, and options. This improves maintainability and makes it easier to add future passes, such as those for vendor-specific extensions or the Zcmt instruction set extension.
- Relaxation
- In the context of linkers, relaxation is a process of adjusting machine code (e.g., branch offsets) after initial assembly to optimize for different addressing modes or to satisfy relocation constraints.
- Pass table
- A data structure that defines a sequence of operations or passes to be executed. In this case, it lists the different relaxation passes available for the RISC-V target.
- Reloc
- Relocation. A placeholder in object code that indicates where an address or symbol needs to be patched by the linker.
- Zcmt
- A proposed RISC-V instruction set extension related to Control-flow Mitigation Technology, aimed at enhancing security.
- RISC-V
- An open-standard instruction set architecture (ISA) based on RISC principles.