RISC-V: Assorted fixes and (hopefully) improvements
This patch series includes various RISC-V assembler and disassembler fixes and improvements.
This patch series addresses multiple issues in the RISC-V assembler and disassembler, including code redundancy, EEW64 checking, Zvfbfmin implication, and rounding mode handling. It also includes fixes for subset parsing and improvements to error handling. The author seeks maintainer approval for the patches.
In Details
This patch series touches various parts of the RISC-V assembler and disassembler within binutils. It involves modifications to instruction parsing (riscv_ip), feature flag handling (Zvfbfwma, Zdinx), and error handling within the RISC-V specific code in bfd and gas. Several patches address corner cases and potential vulnerabilities in the subset parsing logic.
For Context
The binutils project provides essential tools for working with binary files, including the assembler (which translates assembly code into machine code) and the disassembler (which does the reverse). This series of patches focuses on improving the RISC-V architecture support within binutils by fixing bugs, enhancing feature detection, and improving the overall robustness of the assembler and disassembler.