RISC-V: drop FCVT.Q.L{,U} forms with rounding mode operand
Removes the rounding mode operand from the `FCVT.Q.L` and `FCVT.Q.LU` RISC-V instructions as it has no effect.
This patch removes the rounding mode operand from the FCVT.Q.L and FCVT.Q.LU RISC-V instructions in the opcode table. The rounding mode has no effect on these instructions, so allowing the operand is misleading. This change aligns these instructions with similar ones (FCVT.D.W, FCVT.Q.W) and simplifies the opcode definitions.
In Details
The RISC-V opcode table in opcodes/riscv-opc.c defines the format of RISC-V instructions. This patch removes the rounding mode ('m') operand from the FCVT.Q.L and FCVT.Q.LU instruction definitions because these instructions are unaffected by the rounding mode. This change simplifies the opcode table and avoids potential confusion.
For Context
The instruction set architecture (ISA) defines the instructions a CPU can execute. RISC-V is a modern open ISA designed for a wide range of applications. Instructions can have operands that specify the data to be operated on. Rounding modes specify how floating-point numbers should be rounded to fit within a certain precision. This patch removes an unnecessary operand from certain RISC-V instructions, simplifying the instruction definition.