RISC-V: Add support for ARC-V APEX assembler
This patch adds support for the ARC-V APEX extension, allowing dynamic custom instruction definition in the RISC-V assembler.
This patch introduces support for ARC-V APEX (ARC Processor EXtension) to the RISC-V assembler. APEX enables users to dynamically define custom instructions using the Custom-0 encoding space. The patch implements the .extInstruction directive for registering new instructions, which emit metadata into a COMDAT ELF section. This allows instruction definitions to be preserved in the linked object.
- proposer
Proposes adding ARC-V APEX assembler support, which allows users to define custom instructions dynamically.
“Add support for ARC-V APEX (ARC Processor EXtension), which allows users to dynamically define custom instructions that use the Custom-0 encoding space.”
In Details
This patch adds support for ARC-V APEX to the RISC-V assembler. APEX allows users to dynamically define custom instructions that use the Custom-0 encoding space. The implementation involves adding a new directive, .extInstruction, and emitting metadata records into a COMDAT ELF section. This allows instruction definitions to be preserved in the linked object.
For Context
The GNU Assembler (GAS) translates assembly code into machine code. This patch adds support for the ARC-V APEX extension to the RISC-V assembler. APEX allows developers to create their own custom instructions, extending the base RISC-V instruction set. This patch introduces a new directive called .extInstruction that allows developers to define these custom instructions within their assembly code.