RISC-V: Add support for ARC-V APEX disassembler
This patch adds disassembler support for ARC-V APEX instructions by reading metadata from ELF sections.
This patch adds support to the RISC-V disassembler for ARC-V APEX instructions. The disassembler reads metadata from .riscvapex.* ELF sections (emitted by the assembler) to reconstruct instruction definitions at startup. The metadata is deserialized into a lookup table, and the disassembler attempts to decode instructions using this table when the standard opcode table produces no match.
- proposer
Proposes adding ARC-V APEX disassembler support by reading metadata from ELF sections.
“Add disassembler support for ARC-V APEX instructions by reading metadata from .riscvapex.* ELF sections (emitted by GAS) and reconstructing instruction definitions at startup.”
In Details
This patch adds ARC-V APEX disassembler support. It reads metadata from .riscvapex.* ELF sections, emitted by the assembler, and reconstructs instruction definitions at startup. The disassembler uses this metadata to decode APEX instructions when the standard opcode table fails.
For Context
A disassembler translates machine code back into human-readable assembly code. This patch extends the RISC-V disassembler to support ARC-V APEX, a feature that allows custom instructions. The disassembler reads information about these custom instructions (metadata) embedded in the compiled program to correctly translate them back into assembly code.